1. Field of the Invention
The present invention relates generally to packet collecting circuits, and more particularly, to packet collecting circuits for use in data-flow type system.
2. Description of the Background Art
In a data-flow type system, data flows in synchronization with pulse signals transmitted through the system and corresponding processing is carried out on the data which is subsequently shifted. FIG. 8 is a block diagram showing a structure of a data transmission path for transmitting data in the data-flow type system.
The data transmission path includes a self-synchronous type transfer control circuit 1 and a data hold circuit 2 comprised of a D type flip-flop. The transfer control circuit 1 has a pulse input terminal CI for receiving a pulse from a preceding stage portion (not shown), a transfer acknowledging (permitting) output terminal RO for outputting a transfer acknowledging (permitting) signal indicative of permission or inhibition of transfer to the preceding stage portion, a pulse output terminal CO for outputting a pulse to a succeeding stage portion (not shown) and a transfer acknowledging input terminal RI for receiving a transfer acknowledging signal indicative of permission or inhibition of transfer from the succeeding stage portion. The transfer control circuit 1, on receiving a pulse from the preceding stage portion, outputs pulses to the succeeding stage portion and to the data hold circuit 2 when a transfer acknowledging signal from the succeeding stage portion is in a permitted state. The data hold circuit 2 holds data DI applied from the preceding stage portion and applies the held data to the succeeding stage portion as output data DO in response to the pulse applied from the transfer control circuit 1.
In the data-flow type system, data and pulses are sequentially transferred through a plurality of data transmission paths of the structure shown in FIG. 9 connected in series.
An interleave processing system is adopted for such a relatively time consuming single processing as memory access. The interleave processing system employs a packet distributing circuit 3 and a packet collecting circuit 4 as shown in FIG. 9. The packet distributing circuit 3 distributes pulses and data packets applied to an input terminal 1 among a plurality of processing circuits 5. The packet collecting circuit 4 collects pulses and data packets applied from the plurality of processing circuits 5 and outputs the same to an output terminal 0 in a predetermined order. The packet collecting circuit 4 includes a plurality of merging circuits.
FIG. 10 is a block diagram showing a structure of one merging circuit included in the packet collecting circuit 4. The merging circuit includes a pulse control circuit 41 and a data selector 42.
The pulse control circuit 41 has first and second pulse input terminals CIa and CIb for receiving two asynchronous input pulses, a pulse output terminal CO for outputting pulses and a selector SEL for outputting a select signal. The data selector 42 has first and second data input terminals DIa and DIb for receiving two asynchronous data packets, a data output terminal DO for outputting data packets and a selector terminal SEL for receiving a select signal.
On receiving two asynchronous input pulses at the first and the second pulse input terminals CIa and CIb, the pulse control circuit 41 outputs a select signal indicative of a value corresponding to the first received pulse through the selector terminal SEL and outputs a pulse through the pulse output terminal CO at the same time. The data selector 42 outputs one of the data packets applied to the first and second data input terminals DIa and DIb through the data output terminal DO in response to the select signal.
After the lapse of a predetermined time, the pulse control circuit 41 outputs a select signal indicative of a value corresponding to the second received pulse through the selector terminal SEL and at the same time outputs a pulse to the pulse output terminal CO. The data selector 42 outputs the other of the data packets applied to the first and the second data input terminals DIa and DIb through the data output terminal DO in response to the select signal.
As described in the foregoing, the pulse control circuit 41 controls the data selector 42 such that the data packets are transferred in the order of arrival.
The merging circuit of FIG. 10 collects data packets flowing through a first packet flow path constituted by the first pulse input terminal CIa and the first data input terminal DIa and data packets flowing through a second packet flow path constituted by the second pulse input terminal CIb and the second data input terminal DIb, which data packets are output to a packet flow path constituted by the pulse output terminal CO and the data output terminal DO.
The packet collecting circuit 4 of FIG. 9 constituted by the merging circuit of FIG. 10 produces an effect that data packets flowing through a plurality of packet flow paths are equally merged.
However, for collecting data packets flowing through eight packet flow paths, for example, seven merging circuits are required. A circuit scale is extremely increased.
In addition, while data packets flowing through a plurality of packet flow paths are merged equally, it is not possible to control the order of data packet trains output from a packet collecting circuit. It is therefore impossible to keep the order of data packet trains output from a packet collecting circuit. It is therefore impossible to keep the order of data packets to be applied to the input terminal of the packet distributing circuit 3 shown in FIG. 9.